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DIGITAL CIRCUITS

Module by: Dinh Sy Hien

Summary: This module presents the basic concepts of MOSFET digital logic circuits. We will examine NMOS logic circuits, which contain only n-channel transistors, and complementary MOS, or CMOS, logic circuits, which contain both n-channel and p-channel transistors. The NMOS inverter is the basic of NMOS digital logic circuits. We will analyze the dc voltage transfer characteristics of several inverter designs. We will also define and develop the noise margin of NMOS digital circuits in terms of the inverter voltage transfer curve. We will then determine the impact of the body effect on the dc voltage transfer curve and the logic levels. A transient analysis of the NMOS inverter will determine the propagation delay time in NMOS logic circuits. We will then develop and analyze basic NMOS NOR and NAND logic gates, as well as circuits that perform more complex logic functions. The CMOS inverter is the basic of CMOS logic gates. We will analyze the inverter dc voltage transfer characteristics, and will determine the power dissipation in the CMOS inverter, demonstrating the principle advantage of CMOS inverter over NMOS circuits. Next, we will develop the noise margin of the CMOS inverter, and then will develop and analyze basic CMOS NOR and NAND logic gates. Finally, we will look at more advanced clocked CMOS logic circuits which eliminate almost half of transistors in a conventional CMOS logic design while maintaining the low power advantage of the CMOS technology. In a digital system, a transistor can act as a switch between a driving circuit and a load circuit. An NMOS transistor that performs this function is called an NMOS transmission gate; the corresponding CMOS configuration is a CMOS transmission gate. These transmission gates, or pass transistors, can also be configured to perform logic functions, and the circuits are called NMOS-pass or CMOS-pass networks. We will discuss the basics of these networks. Finally in this module, we will consider a few examples of sequential logic circuits. Two dynamic shift registers are defined and analyzed, and a static R-S flip-flop are defined and analyzed.

This module presents the basic concepts of MOSFET digital logic circuits. We will examine NMOS logic circuits, which contain only n-channel transistors, and complementary MOS, or CMOS, logic circuits, which contain both n-channel and p-channel transistors. JFET logic circuits are very specialized and therefore not considered here.
The NMOS inverter is the basic of NMOS digital logic circuits. We will analyze the dc voltage transfer characteristics of several inverter designs. We will also define and develop the noise margin of NMOS digital circuits in terms of the inverter voltage transfer curve. We will then determine the impact of the body effect on the dc voltage transfer curve and the logic levels. A transient analysis of the NMOS inverter will determine the propagation delay time in NMOS logic circuits. We will then develop and analyze basic NMOS NOR and NAND logic gates, as well as circuits that perform more complex logic functions.
The CMOS inverter is the basic of CMOS logic gates. We will analyze the inverter dc voltage transfer characteristics, and will determine the power dissipation in the CMOS inverter, demonstrating the principle advantage of CMOS inverter over NMOS circuits. Next, we will develop the noise margin of the CMOS inverter, and then will develop and analyze basic CMOS NOR and NAND logic gates. Finally, we will look at more advanced clocked CMOS logic circuits which eliminate almost half of transistors in a conventional CMOS logic design while maintaining the low power advantage of the CMOS technology.
In a digital system, a transistor can act as a switch between a driving circuit and a load circuit. An NMOS transistor that performs this function is called an NMOS transmission gate; the corresponding CMOS configuration is a CMOS transmission gate. These transmission gates, or pass transistors, can also be configured to perform logic functions, and the circuits are called NMOS-pass or CMOS-pass networks. We will discuss the basics of these networks.
Finally in this module, we will consider a few examples of sequential logic circuits. Two dynamic shift registers are defined and analyzed, and a static R-S flip-flop are defined and analyzed.

NMOS INVERTERS

The inverter is the basic circuit of most MOS logic circuits. The design techniques used in NMOS logic circuits are developed from the dc analysis results for NMOS inverter. Extending the concepts developed from the inverter to NOR and NAND gates is then direct. Alternative inverter load elements are compared in terms of power consumption, packing density, and transfer characteristics. The transient analysis and switching characteristics of the inverters give an indication of the propagation delay times of NMOS logic circuits.

n-Channel MOSFET

In this section, we will quickly review the n-channel MOSFET characteristics, emphasizing specific properties important in digital circuit design.
A simplified n-channel MOSFET is shown in Figure 1. The body or substrate, is a single crystal silicon wafer which is the starting material for circuit fabrication and provides physical support for the integrated circuit. The active transistor region is the surface of the semiconductor and is comprised of the heavy doped n+n+ size 12{n rSup { size 8{+{}} } } {} source and drain regions and p-type channel region. The channel length is L and the channel width is W. normally, in any given fabrication process, the channel length is the same for all transistors, while the channel width is variable.
Figure 1: a) n-chanel MOSFET simplified view and b)n-channel MOSFET detailed cross section
Figure 1b shows a more detailed view of the n-channel MOSFET. This figure demonstrates that the actual device geometry is more complicated than that indicated by the simplified cross section.
Figure 2: a) Simplified circuit symbols for n-channel MOSFETs and b) circuit symbols showing substrate or body terminal
Figure 2a shows the simplified circuit symbols for the n-channel enhancement and depletion-mode devices. When we explicitly consider the body or substrate connection, we will use the symbols shows in Figure 2b.
In an integrated circuit, all n-channel transistors are fabricated in the same p-type substrate material. The substrate is connected to the most negative potential in the circuit, which for digital circuits, is normally at ground potential or zero volts. However, the source terminal of many of transistors will not be at zero volts, which means that a reverse-biased pn junction will exist between source and substrate.
When the source and body terminal are connected together, the threshold voltage, to a first approximation, is independent of the applied voltages. However, when the source and body voltages are not equal, as when transistors are used for active loads, for instance, the threshold voltage is a function of difference between these voltages. We can write
V Th = V Th 0 + 2eε s N a C ox [ 2φ fp + V SB − 2φ fp ] = V Th 0 + γ [ 2φ fp + V SB − 2φ fp ] V Th = V Th 0 + 2eε s N a C ox [ 2φ fp + V SB − 2φ fp ] = V Th 0 + γ [ 2φ fp + V SB − 2φ fp ] size 12{V rSub { size 8{ ital "Th"} } =V rSub { size 8{ ital "Th"0} } + { { sqrt {2eε rSub { size 8{s} } N rSub { size 8{a} } } } over {C rSub { size 8{ ital "ox"} } } } \[ sqrt {2φ rSub { size 8{ ital "fp"} } +V rSub { size 8{ ital "SB"} } } - sqrt {2φ rSub { size 8{ ital "fp"} } } \] =V rSub { size 8{ ital "Th"0} } +γ \[ sqrt {2φ rSub { size 8{ ital "fp"} } +V rSub { size 8{ ital "SB"} } } - sqrt {2φ rSub { size 8{ ital "fp"} } } \] } {} (1)
where VSBVSB size 12{V rSub { size 8{ ital "SB"} } } {} is the source-to-body voltage, and VTh0VTh0 size 12{V rSub { size 8{ ital "Th"0} } } {} is the threshold voltage for zero source-to-body voltage or VSB=0VSB=0 size 12{V rSub { size 8{ ital "SB"} } =0} {}. The parameter NaNa size 12{N rSub { size 8{a} } } {} is the p-type substrate doping concentration, εsεs size 12{ε rSub { size 8{s} } } {} is the semiconductor permittivity, CoxCox size 12{C rSub { size 8{ ital "ox"} } } {} is the oxide capacitance per unit area, φfpφfp size 12{φ rSub { size 8{ ital "fp"} } } {} is a potential related to the substrate doping concentration, and γγ size 12{γ} {} is the body-effect coefficient.
The current-voltage characteristics of the n-channel MOSFET are functions of both the electrical and geometrical properties of the device. When the transistor is biased in the nonsaturation region, for vGS≥VThvGS≥VTh size 12{v rSub { size 8{ ital "GS"} } >= V rSub { size 8{ ital "Th"} } } {} and vDS≤(vGS−VTh)vDS≤(vGS−VTh) size 12{v rSub { size 8{ ital "DS"} } <= \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) } {}, we can write
i D = k n [ 2 ( V GS − V Th ) v DS − v DS 2 ] i D = k n [ 2 ( V GS − V Th ) v DS − v DS 2 ] size 12{i rSub { size 8{D} } =k rSub { size 8{n} } \[ 2 \( V rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) v rSub { size 8{ ital "DS"} } - v rSub { size 8{ ital "DS"} } rSup { size 8{2} } \] } {} (2)
In the saturation region, for vGS≥VThvGS≥VTh size 12{v rSub { size 8{ ital "GS"} } >= V rSub { size 8{ ital "Th"} } } {}, and vDS≥(vGS−VTh)vDS≥(vGS−VTh) size 12{v rSub { size 8{ ital "DS"} } >= \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) } {}, we have
i D = k n ( v GS − V Th ) 2 i D = k n ( v GS − V Th ) 2 size 12{i rSub { size 8{D} } =k rSub { size 8{n} } \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } } {} (3)
The transition point separates the non-saturation and saturation regions and is the drain-to-source saturation voltage which is given by
v DS = v DS ( sat ) = v GS − V Th v DS = v DS ( sat ) = v GS − V Th size 12{v rSub { size 8{ ital "DS"} } =v rSub { size 8{ ital "DS"} } \( ital "sat" \) =v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } } {} (4)
The term (1+λvDS)(1+λvDS) size 12{ \( 1+λv rSub { size 8{ ital "DS"} } \) } {} is sometimes included in Equation 4b to account for channel length modulation and the finite output resistance. In most cases, it has little effect on the operating characteristics of MOS digital circuits. In our analysis, the term λλ size 12{λ} {} is assumed to be zero unless otherwise stated.
The parameter knkn size 12{k rSub { size 8{n} } } {} is the NMOS transistor conduction parameter and is given by
k n = ( 1 2 μ n C ox ) ( W L ) = k n ' 2 W L k n = ( 1 2 μ n C ox ) ( W L ) = k n ' 2 W L size 12{k rSub { size 8{n} } = \( { {1} over {2} } μ rSub { size 8{n} } C rSub { size 8{ ital "ox"} } \) \( { {W} over {L} } \) = { {k rSub { size 8{n} } rSup { size 8{'} } } over {2} } { {W} over {L} } } {} (5)
The electron mobility μnμn size 12{μ rSub { size 8{n} } } {} and oxide capacitance C0xC0x size 12{C rSub { size 8{0x} } } {} are assumed to be constant for all devices in a particular IC.
The current-voltage characteristics are directly related to the channel width-to-length ratio, or the size of the transistor. In general, in a given IC, the length L is fixed, but the designer can control the channel width W.
Since the MOS transistor is a majority carrier device, the switching speed of MOS digital circuits is limited by the time required to charge or discharge the capacitances between device electrodes and between interconnect lines and ground. Figure 3 shows the significant capacitances in a MOSFET. The capacitances CsbCsb size 12{C rSub { size 8{ ital "sb"} } } {} and CdbCdb size 12{C rSub { size 8{ ital "db"} } } {} are the source-to-body and drain-to-body n+n+ size 12{n rSup { size 8{+{}} } } {}p junction capacitances. The total input gate capacitance, to a first approximation, is a constant equal to
C g = WLC ox = WL ( ε ox t ox ) C g = WLC ox = WL ( ε ox t ox ) size 12{C rSub { size 8{g} } = ital "WLC" rSub { size 8{ ital "ox"} } = ital "WL" \( { {ε rSub { size 8{ ital "ox"} } } over {t rSub { size 8{ ital "ox"} } } } \) } {} (6)
where C0xC0x size 12{C rSub { size 8{0x} } } {} is the oxide capacitance per unit area, and is a function of the oxide thickness. The parameter C0xC0x size 12{C rSub { size 8{0x} } } {} also appears in the expression for the conduction parameter.
Figure 3: n-channel MOSFET and device capacitances

NMOS Inverter Transfer Characteristics

Since the inverter is the basic for most logic circuits, we will describe the NMOS inverter and will develop the dc transfer characteristics for three types of inverters with different load devices. This discussion will introduce voltage transfer functions, noise margins, and the transient characteristics of FET digital circuits.
NMOS inverter with resistor load
Figure 4a shows a single NMOS transistor connected to a resistor to form an inverter. The transistor characteristics and load line are shown in Figure 4b, along with the parametric curve separating the saturation and nonsaturation regions. We determine the voltage transfer characteristics of the inverter by examining the various regions in which the transistor can be biased.
Figure 4: a) NMOS inverter with resistor load and b) transistor characteristics and load line
When the input voltage is less than or equal to the threshold, or vI≤VThvI≤VTh size 12{v rSub { size 8{I} } <= V rSub { size 8{ ital "Th"} } } {}, the transistor is cut off, iD=0iD=0 size 12{i rSub { size 8{D} } =0} {}, and the output voltage is v0=VDDv0=VDD size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } } {}. The maximum output voltage is defined as the logic 1 level. As the input voltage becomes just greater than VThVTh size 12{V rSub { size 8{ ital "Th"} } } {}, the transistor turns on and is biased in the saturation region. The output voltage is than
v 0 = V DD − i D R D v 0 = V DD − i D R D size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } - i rSub { size 8{D} } R rSub { size 8{D} } } {} (7)
Where the drain current is given by
i D = k n ( v GS − V Th ) 2 = k n ( v I − V Th ) 2 i D = k n ( v GS − V Th ) 2 = k n ( v I − V Th ) 2 size 12{i rSub { size 8{D} } =k rSub { size 8{n} } \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } =k rSub { size 8{n} } \( v rSub { size 8{I} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } } {} (8)
Combining Equation 7 and (Reference) yields
v 0 = V DD − k n R D ( v I − V Th ) 2 v 0 = V DD − k n R D ( v I − V Th ) 2 size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } - k rSub { size 8{n} } R rSub { size 8{D} } \( v rSub { size 8{I} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } } {} (9)
which relates the output and input voltages as long as the transistor is biased in the saturation region.
As the input voltage increases, the Q-point of the transistor moves up the load line. At the transition point, we have
V 0t = V It − V Th V 0t = V It − V Th size 12{V rSub { size 8{0t} } =V rSub { size 8{ ital "It"} } - V rSub { size 8{ ital "Th"} } } {} (10)
where V0tV0t size 12{V rSub { size 8{0t} } } {} and VItVIt size 12{V rSub { size 8{ ital "It"} } } {} are the drain-to-source and gate-to-source voltage, respectively, at the transition point. Substituting Equation 10 into Equation 9, the input voltage at the transition point is the determined from
K n R D ( V It − V Th ) 2 + ( V D − V Th ) − V DD = 0 K n R D ( V It − V Th ) 2 + ( V D − V Th ) − V DD = 0 size 12{K rSub { size 8{n} } R rSub { size 8{D} } \( V rSub { size 8{ ital "It"} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } + \( V rSub { size 8{D} } - V rSub { size 8{ ital "Th"} } \) - V rSub { size 8{ ital "DD"} } =0} {} (11)
As the input voltage becomes greater than VItVIt size 12{V rSub { size 8{ ital "It"} } } {}, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region. The drain current is then
i D = k n 2 ( v GS − V Th ) v DS − v DS 2 = k n 2 ( v I − V Th ) v 0 − v 0 2 i D = k n 2 ( v GS − V Th ) v DS − v DS 2 = k n 2 ( v I − V Th ) v 0 − v 0 2 size 12{i rSub { size 8{D} } =k rSub { size 8{n} } left [2 \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) v rSub { size 8{ ital "DS"} } - v rSub { size 8{ ital "DS"} } rSup { size 8{2} } right ]=k rSub { size 8{n} } left [2 \( v rSub { size 8{I} } - V rSub { size 8{ ital "Th"} } \) v"" lSub { size 8{0} } - v rSub { size 8{0} } rSup { size 8{2} } right ]} {} (12)
Combining Equation 7 and Equation 12 yields
v 0 = V DD − k n R D [ 2 ( v I − V Th ) v 0 − v 0 2 ] v 0 = V DD − k n R D [ 2 ( v I − V Th ) v 0 − v 0 2 ] size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } - k rSub { size 8{n} } R rSub { size 8{D} } \[ 2 \( v rSub { size 8{I} } - V rSub { size 8{ ital "Th"} } \) v"" lSub { size 8{0} } - v rSub { size 8{0} } rSup { size 8{2} } \] } {} (13)
Which relates to the input and output voltage as long as the transistor is biased in the nonsaturation region.
Figure 5 shows the voltage transfer characteristics of this inverter for three resistor values. Also shown is the line, given by Equation 10, which separates the saturation and nonsaturation bias region of the transistor. The figure shows that the minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance, and the sharpness of the transition region between a low input and a high input increases with increasing load resistance.
Figure 5: Voltage transfer characteristics, NMOS inverter with resistor load, for three resistor values
It should be note that a large resistance is difficult to fabricate in an IC. A large resistor value in the inverter will limit current and power consumption as well as provide a small VOLVOL size 12{V rSub { size 8{ ital "OL"} } } {} value. But it would also require a large chip area if fabricated in a standard MOS process. To avoid this problem, MOS transistors can be used as load devices, replacing the resistor, as discussed in subsequent paragraphs.
NMOS inverter with enhancement load
An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as a load device in an NMOS inverter. Figure 6a shows such a device. For vGS=vDS≤VThvGS=vDS≤VTh size 12{v rSub { size 8{ ital "GS"} } =v rSub { size 8{ ital "DS"} } <= V rSub { size 8{ ital "Th"} } } {}, the drain current is zero. For vGS=vDS≥VThvGS=vDS≥VTh size 12{v rSub { size 8{ ital "GS"} } =v rSub { size 8{ ital "DS"} } >= V rSub { size 8{ ital "Th"} } } {}, a nonzero drain current is induced in the device. We can see that the following condition is satisfied:
v DS > ( v GS − V Th ) = ( v DS − V Th ) = v DS ( sat ) v DS