Having understood the fundamental laws of circuit theory (Ohm’s law and Kirchhhoff’s laws), we are now prepared to apply to develop two powerful techniques for circuit analysis: nodal analysis, which is based on a systematic application of Kirchhoff’s current law (KCL) and mesh analysis which based on a systematic application of Kirchhoff’s voltage law (KVL). The two techniques are so important that this chapter should be regarded as the most important in the book. Students are therefore encouraged to pay careful attention.

With the two techniques to be developed in this chapter we can analyze any linear circuit by obtaining a set of simultaneous equation that are then solved to obtain the required values of current or voltage. One method of solving simultaneous equations involves Cramer’s rule, which allow us to calculate circuit variables as a quotient of determinants.

Finally, we apply the technique learned in this chapter to analyze transistor circuits.

Nodal analysis provides a general procedure circuits using node voltages as the circuit variables. Choosing node voltages instead of element voltages as circuit variables is convenient and reduces the number of equations one must solve simultaneously.

To simplify matters, we shall assume in this section that circuits do not contain voltage sources. Circuits that contain voltage sources will be analyzed in the next section.

In nodal analysis, we are interested in finding the node voltages. Given a circuit with n nods without voltage sources, the nodal analysis of the circuit involves taking the following three steps.

2. Apply KCL to each of the n-1 nonreference nodes. Use Ohm’s law to express the branch currents in term of node voltages.

3. Solve the resulting simultaneous equations to obtain the unknown node voltages.

We shall now explain and apply these three steps.

The first step in nodal analysis is selecting a node as the reference or datum node. The reference node is commonly called the ground since it is assumed to have zero potential. A reference node is indicated by any of the three symbols in Figure 1. The type of ground in Figure 1(b) is called a chassis ground and is used in devices where the case, enclosure, or chassis acts as reference point for all circuits. When the potential of the earth is used as reference, we use the earth ground in Figure 1(a) or Figure 1(c). We shall always use the symbol in Figure 1(b).

Once we have selected a reference node, we assign voltage designations to nonreference nodes. Consider, for example, the circuit in Figure 2(a). Node 0 is the reference node (v = 0), while nodes 1 and 2 are assigned voltages v1v1 size 12{v rSub { size 8{1} } } {} and v2v2 size 12{v rSub { size 8{2} } } {}, respectively. Keep in mind that the node voltages are defined with respect to the reference node. As illustrated in Figure 1(a) each node voltage is the voltage rise from the reference node to the corresponding nonreference node or simply the voltage of that node with respect to the reference node.

As the second step, we apply KCL to each nonreference node in the circuit. To avoid putting too much information on the same circuit, the circuit in Figure 2(a) is redrawn in Figure 2(b), where we now add i1i1 size 12{i rSub { size 8{1} } } {}, i2i2 size 12{i rSub { size 8{2} } } {}, and i3i3 size 12{i rSub { size 8{3} } } {} as the circuits through resistors R1R1 size 12{R rSub { size 8{1} } } {}, R2R2 size 12{R rSub { size 8{2} } } {}, and R3R3 size 12{R rSub { size 8{3} } } {}, respectively. At node 1, applying KCL gives

At node 2,

We now apply Ohm’s to express the unknown currents i1i1 size 12{i rSub { size 8{1} } } {}, i2i2 size 12{i rSub { size 8{2} } } {}, and i3i3 size 12{i rSub { size 8{3} } } {} in term of node voltages. The key idea to bear in mind is that, since resistance is a passive element, by the passive sign convention, current must always flow from a higher potential to a lower potential.

We can express this principle as

Note that this principle is in agreement with the way we define resistance in chapter 2 (see Figure 2.1). With this in mind, we obtain from Figure 2(b),

i1=v1−0R1i1=v1−0R1 size 12{i rSub { size 8{1} } = { {v rSub { size 8{1} } - 0} over {R rSub { size 8{1} } } } } {}or i1=G1v1i1=G1v1 size 12{i rSub { size 8{1} } =G rSub { size 8{1} } v rSub { size 8{1} } } {}

or

i3=v2−0R3i3=v2−0R3 size 12{i rSub { size 8{3} } = { {v rSub { size 8{2} } - 0} over {R rSub { size 8{3} } } } } {}or I3=G3v2I3=G3v2 size 12{I rSub { size 8{3} } =G rSub { size 8{3} } v rSub { size 8{2} } } {}

Substituting Equation 4 in Equation 1 and Equation 2 results, respectively, in

In terms of the conductances, Equation 5 and Equation 6 become

The third step in nodal analysis is to solve for the node voltages. If we apply KCL to n-1 nonreference nodes, we obtain n-1 simultaneous equations such as Equation 5 and Equation 6 or Equation 7 and Equation 8. For the circuit of Figure 2, we solve Equation 5 and Equation 6 or Equation 7 and Equation 8 to obtain the node voltages v1v1 size 12{v rSub { size 8{1} } } {} and v2v2 size 12{v rSub { size 8{2} } } {} using any standard method, such as substitution method, elimination method, Cramer’s rule or matrix inversion. To use either of the last two methods, one must cast the simultaneous equations in matrix form. For example, Equation 7 and Equation 8 can be cast in matrix form as

which can be solved to get v1v1 size 12{v rSub { size 8{1} } } {} and v2v2 size 12{v rSub { size 8{2} } } {}. (Reference) will be generalized in section 6. The simultaneous equations may also be solved using calculator or with software package such as MATLAB.

We now consider how voltage sources effect nodal analysis. We use the circuit in Figure 3 for illustration. Consider the following two possibilities.

CASE 1: if a voltage source is connected between the reference node and a nonreference node, we supply set the voltage at the nonreference node equal to the voltage of the voltage source. In Figure 3, for example,

Thus our analysis is somewhat simplified by this knowledge of the voltage at this node.

CASE 2: If the voltage source (dependent or independent) is connected between two nonreference nodes, the two nonreference nodes form a generalized node or supernode; we apply both KCL and KVL to determine the node voltages.

In Figure 3, nodes 2 and 3 form a supernode. We analyze a circuit with supernode using the same three steps mentioned in the previous section except that the supernodes are treated differently. Why? Because an essential component of nodal analysis is applying KCL, which requires knowing the current through each element. There is no way of knowing the current through a voltage source in advance. However, KCL must be satisfied at a supernode like any other node. Hence, at the supernode in Figure 3,

or

To apply Kirchhoff’s voltage law to the supernode in Figure 3, we redraw the circuit as shown in Figure 4. Going around the loop in the clockwise direction gives

From Equation 10, Equation 12 and Equation 13, we obtain the node voltages.

Note the following properties of a supernode:

1. The voltage source inside the supernode provides a constraint equation needed to solve for the node voltage.

2. A supernode has no voltage of it own.

3. A supernode requires the application of both KCL and KVL.

Mesh analysis is also known as loop analysis or the mesh current method. Mesh analysis provides another general procedure for analyzing circuits using mesh currents as the circuit variables. Using mesh currents instead of element currents as circuit variables is convenient and reduces the number of equations that must be solved simultaneously. Recall that a loop is closed path with no node passed more than once. A mesh is a loop that does not contain any other loop within it.

Nodal analysis applies KCL to find unknown voltages in a given circuit, while mesh analysis applies KVL to find unknown currents. Mesh analysis is not quite as general as nodal analysis because it is only applicable to a circuit that is planar. A planar circuit is one that can be drawn in a plane with no branches crossing one another; otherwise it is nonplanar. A circuit may have crossing branches and still be planar if it can be redrawn such that it has no crossing branches. For example, the circuit in Figure 5(a) has two crossing branches, but it can be redrawn as in Figure 5(b). Hence, the circuit in Figure 5(a) is planar. However, the circuit in Figure 6 is nonplanar, because there is no way to redraw it and avoid the branches crossing. Nonplanar circuits can be handled using mesh analysis, but they will not be considered in this text.

To understand mesh analysis, we should first explain more about what we mean by a mesh.

In Figure 7, for example, paths abefa and bcdeb are meshes, but path abcdefa is not a mesh. The current through a mesh is known as mesh current. In mesh analysis, we are interested in applying KVL to find the mesh currents in a given circuit.

In this section, we will apply mesh analysis to planar circuits that do not contain current sources. In the next section, we will consider circuits with current sources. In the mesh analysis of a circuit with n meshes, we take the following three steps.

To illustrate the steps, consider the circuit in Figure 7. The first step requires that mesh currents i1i1 size 12{i rSub { size 8{1} } } {} and i2i2 size 12{i rSub { size 8{2} } } {} are assigned to meshes 1 and 2. Although a mesh current may be assigned to each mesh in arbitrary direction, it is conventional to assume that each mesh current flows clockwise.

As the second step, we apply KVL to each mesh. Applying KVL to mesh 1, we obtain

− V 1 + R 1 I 1 + R 3 ( i 1 − i 2 ) = 0 − V 1 + R 1 I 1 + R 3 ( i 1 − i 2 ) = 0 size 12{ - V rSub { size 8{1} } +R rSub { size 8{1} } I rSub { size 8{1} } +R rSub { size 8{3} } \( i rSub { size 8{1} } - i rSub { size 8{2} } \) =0} {}

Or

For mesh 2, applying KVL gives

R 2 i 2 + V 2 + R 3 ( i 1 − i 2 ) = 0 R 2 i 2 + V 2 + R 3 ( i 1 − i 2 ) = 0 size 12{R rSub { size 8{2} } i rSub { size 8{2} } +V rSub { size 8{2} } +R rSub { size 8{3} } \( i rSub { size 8{1} } - i rSub { size 8{2} } \) =0} {}

or

The third step is to solve for the mesh currents. Putting Equation 14 and Equation 15 in matrix form yields

Notice that the branch currents are different from the mesh current unless the mesh is isolated. To distinguish between the two types of currents, we use i for a mesh current and I for a branch current. The current elements I1I1 size 12{I rSub { size 8{1} } } {}, I2I2 size 12{I rSub { size 8{2} } } {}, and I3I3 size 12{I rSub { size 8{3} } } {} are algebraic sums of the mesh currents. It is evident from Figure 7 that

I2=i2I2=i2 size 12{I rSub { size 8{2} } =i rSub { size 8{2} } } {}, I3=i1−i2I3=i1−i2 size 12{I rSub { size 8{3} } =i rSub { size 8{1} } - i rSub { size 8{2} } } {}

Applying mesh analysis to circuits containing current sources (dependent or independent) may appear complicated. But it is actually much easier than what we encountered in the previous section, because the presence of the current sources reduces the number of equations. Consider the following two possible cases.

CASE 1. When a current source exists only in one mesh: consider the circuit in Figure 8, for example. We set i2=−5Ai2=−5A size 12{i rSub { size 8{2} } = - 5A} {} and write a mesh equation for the other mesh in the usual way, that is,

CASE 2. When a current source exists between two meshes: consider the circuit in Figure 9(a), for example. We create a supermesh by excluding the current source and any elements connected in series with it, as shown in Figure 9(b). Thus,

As shown in Figure 9(b), we create a supermesh as the periphery of the two meshes and treat it differently. If a circuit has two or more supermeshes that intersect, they should be combined to form a larger supermesh. Why treat the supermesh differently? Because mesh analysis applies KVL-which requires that we know the voltage across each branch-and we do not know the voltage across a current source in advance. However, a supermesh must satisfy KVL like any other mesh. Therefore, applying KVL to the supermesh in Figure 9(b) gives

− 20 + 6i 1 +